Terasic’s DE0-Nano
The Terasic DE0-Nano is an excellent device, but it lacks an easily accessible UART to get information in and out of your design.
Fortunately, Altera’s Virtual JTAG functionality allows easy access to logic inside of your design. Chris Zeh wrote an excellent article on this Virtual JTAG functionality and how to easily send data in and out of the chip. You can read his blog entry here.
This Virtual UART project is an extension of Chris’s work. It provides a Verilog template to expose a parallel FIFO interface into and out of your design, matched to a TCL script on the PC side. It allows a simple way to talk to your logic design through a character interface – ideal for a terminal interface to your latest NIOS or OpenRISC SoC.
The example TCL script sets up a network connection on your PC, listening on port 2323. Using Telnet to connect to this port will parse the Virtual JTag instructions to get data in and out of the Virtual UART buffers.
The quickest way to get started is to run the pre-compiled images provided here. When you’re ready to incorporate this into your own design, all source is available on Github.
Even with no additional hardware, adding a Virtual UART to your design makes the DE0 Nano even more accessible. If you find this useful, let me know in the comments!
Binary Logic 
Excellent work!
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Hey, great job!
I used your design, and modified the FSM to support the Wishbone interface for the STORM core.
I’m able to successfully transmit data to the computer using the STORM processor on DE0-nano.
But I’m having issues in receiving the data. Seems like when the “in buffer” has only one data, it works fine, otherwise it is “skipping” one character from the buffer. For e.g when I send 123456789\r\n from computer, I receive 13579\n
May be I can use your help to make it perfect?
Hi Ali, thanks for your comment. It sounds like an interesting project. If you send me the HDL file for your modified FSM I’ll take a look and see if I can spot the issue. The buffers themselves are ‘black-boxes’ generated by the Altera megawizard, so it’s could be a signalling issue in to/out of the in buffer.
Yeah, I know the buffers are the Altera’s DCFIFO.
Here is the link of what I have made: http://alyyousuf.com/BinaryLogic/jtag_uart.zip
jtag_uart_controller.vhd has the Wishbone interface.
Hey, download it again, I uploaded the wrong version before by mistake
Hi Ali, good catch. I couldn’t read your code as I’m not had much time with VHDL, but I did manage to replicate your reported issue. I found a bug in the FSM. Essentially the global clock drives the FIFO buffers, with the RD/WR# signals gating the movement of data. I was holding the RD signal down for two clocks, rather than one and so it was missing every other character in the input buffer. I’ve pushed a corrected patch back into GitHub, but if you look at the comparison, it’s just a single line of code that’s moved:
https://github.com/binary-logic/vj-uart/commit/bdfd6772da6f92f6a9fc9836057b2bf896e4789d#diff-d41d8cd98f00b204e9800998ecf8427e
You should be able to update your Wishbone bridge fairly easily.
Good luck.